FIRMA DE EXAMEN Y PARTICIPACIÓN
Entradas
SEMAFORO
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library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity semaforo is generic( min_cnt : integer := 0; max_cnt : integer := 25_000_001; top_cnt : integer := 25_000_000 ); port( clk : in std_logic; reset : in std_logic; --in in std_logic; output : out std_logic_vector(2 downto 0) ); end semaforo; architecture Behavioral of semaforo is -- Build an enumerated type for the state machine type state_type is (s0,s1,s2); -- Registrer to hold the current state signal state: state_type; signal cnt : integer range min_cnt to max_cnt:=0; begin process (clk, reset) begin if reset = '1' then state <= s0; elsif (rising_edge(clk)) then case state is when s0 => if cnt = top_cnt then stat...
BCD
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library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity BCD_CI is Port ( i0 : in STD_LOGIC; i1 : in STD_LOGIC; i2 : in STD_LOGIC; i3 : in STD_LOGIC; a : out STD_LOGIC; b : out STD_LOGIC; c : out STD_LOGIC; d : out STD_LOGIC; e : out STD_LOGIC; f : out STD_LOGIC; g : out STD_LOGIC); end BCD_CI; architecture Behavioral of BCD_CI is component COMPUERTAAND is Port ( A : in STD_LOGIC; B : in STD_LOGIC; S...
8 BITS, ADDER Y SUBTRACTOR
L a implementación de un circuito sumador restador sin restricción de 8bits, en el cual no intereso el la operación que se pida, si esta es suma, este sumador va a realizar la suma de A y B. Si se selecciona resta, este sumador va a realizar el calculo del complemento A1 para el numero B que se ingrese, realizara la suma y si A es mayor a B, el resultado que se obtenga va a ser correcto. Pero si se selecciona resta y el numero B es mayor a A, al resultado que de el sumador se tendrá que calcular el complemento A2 para que de el resultado correcto de la resta, pero en este caso tendrá un bit de salida activo que indicara que el resultado es negativo. PROGAMA EN XILINX XILINX library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity adderandsubstractor is Port ( x1 : in STD_LOGIC; x2 : in STD_LOGIC; x3 : in STD_LOGIC; x4 : in ...
Contador de 0 a 9
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CONTDOR_0_TO_9 IS PORT ( CLICK : IN STD_LOGIC; INI : IN STD_LOGIC; RESET : IN STD_LOGIC; DISPLY : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END CONTDOR_0_TO_9; ARCHITECTURE BEHAVIORAL OF CONTDOR_0_TO_9 IS CONSTANT RETRASO_FIN : INTEGER := 49_999_999; SIGNAL RETRASO : INTEGER RANGE 0 TO RETRASO_FIN :=0; SIGNAL CONTADOR_PRINCIPAL : INTEGER RANGE 0 TO 9 := 0; BEGIN PROCESS(CLK) BEGIN IF RISING_EDGE(CLK) THEN IF RESET = '1' THEN RETRASO <= 0; ...
Contador de 0 A 99
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity CONTADOR_0_99 is Port ( CLK : in STD_LOGIC; INI : in STD_LOGIC; RESET : in STD_LOGIC; DISPLAY : out STD_LOGIC_VECTOR (6 DOWNTO 0); TRANSISTOR : out STD_LOGIC_VECTOR (1 DOWNTO 0) ); end CONTADOR_0_99; architecture Behavioral of CONTADOR_0_99 is TYPE MAQUINA IS (UNIDADES, DECENAS); SIGNAL EDO_PP,EDO_F : MAQUINA:= UNIDADES; CONSTANT CONTA_RETRASO_FIN; INTEGER := 49_999_999; CONSTANT CONTA_SW_FIN ; INTEGER :499_999; SIGNAL CONTA_UNIDADES, CONTA_DECIMAS: INTEGER RANGE 0 TO 9 :=0; SIGNAL CONTA_RETRASO: INTEGER RANGE 0 TO CONTA_RETRASO_FIN :=0; SIGNAL CONTA_SWITCH : INTEGER RANGE 0 TO CONTA_SW_FIN:=; SIGNAL CONTADOR_PRINCIPAL : INTEGER RANGE 0 TO 9 := 0; begin PROCESS (CLK) BEGIN IF RISING_EDGE (CLK) THEN IF RESET = '1' THE...
Examen 3
En esta parte mostramos el armado de un circuito con componentes. Programación en XILINX library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity examen is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; q : out STD_LOGIC; p : out STD_LOGIC); end examen; architecture Behavioral of examen is component compuertand2 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; q : out STD_LOGIC); end component; component compuertaxor is Port ( a : in STD_LOGIC; b : in STD_LOGIC; q : out STD_LOGIC); end...